A proposed method for regulating threshold voltage of gate type transistor, or MOS (Metal-Oxide-Semiconductor) transistor of a flash memory cell, that has a floating gate formed on a semiconductor substrate via a gate insulator film and a control gate formed on the floating gate via gate intervening insulator film includes adjusting threshold voltage of the MOS transistor by varying amount of electron accumulated in the floating gate (see, for example, Patent Document 1). When the threshold voltage of the MOS transistor configuring a flash memory is equal to or lower than preset lower limit, this proposed method adjusts the threshold voltage by applying, for the MOS transistor that the threshold voltage thereof is equal to or lower than the preset lower limit, voltage of 0V to the control gate connected with a word line, drive voltage to a drain connected with a bit line and voltage of 0V to a source to inject electrons to the floating gate. A latch circuit is known for a proposed circuit configured with a plurality of gate-type transistors.